Memory wall? Pin Wall!
There is some discussion about many-cores hitting a “memory wall”. Robin Harris writes about it in his article Many-cores hit the memory wall. But i think most of this article think not for enough. Who says, that you just can have many cores. You can have many-memorycontrollers as well. The future solution for memory is perhaps not the fastest bus. It´s the bus that transport as much data as possible with the fewest possible amount of socket pins. The real wall may be the pin budget of modern processors as the number of memory controllers is limited by the possible connections to the outside world. I don´t think there is a wall at 16 cores in processor design because of memory bandwith mandated by some basic principles, there is just a economic limit of manufacturing costs that prevents you from simply increasing the pin count and thus the numbers memory channels. And so the problem of such articles like Jon Stokes “Analysis: more than 16 cores may well be pointless” is just the point, that they think in x86 technology and x86 economics. And even there he might be only correct when you just multiply the cores. There is a reason for connecting three channels of memory to an Intel Nehalem. At the end the memory-wall discussion is somehow a validation of a Sun technology. You have to do something different. The idea of putting 4 memory controller on a T1 for example. The threading concept in the UltraSPARC T1 and T2 was introduced for a reason, too . The basic idea of this concept was “Live with the limited memory bandwidth and with the latency of memory and make the best out of it”. The T1/T2 just switches to another thread in case of a memory stalled thread.