The TLB bug almost ruined the AMD Phenom franchise. But it looks like if Intel has a similar problem with the Nehalem. According to Fudzilla the Nehalem is haunted by a TLB bug too and refers to the errata document of this processor. It looks like history repeating.
At page 16 of the the Intel Core i7 Processor Extreme Edition Series and Intel® Core™ i7 Processor they write:
AAJ1. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance
of a DTLB Error
Problem:A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the Overflow (bit ) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status register.
Implication: Due to this erratum, the Overflow bit in the MCi_Status register may not be an accurate
indication of multiple occurrences of DTLB errors. There is no other impact to normal
But in the clarification for errata AAJ1 on page 37 of the same document they state:
In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data. Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue.
Doesn´t sound like There is no other impact to normal processor functionality. I don´t think, that this bug has the scale of the AMB TLB bug, but i think customers are a little bit sensitive today when they hear TLB and bug in the same sentence.
Update: AAJ42 on Page 27 is interesting, too:
Under certain conditions when C6 and two logical processors on the same core are enabled on a processor, an instruction fetch occurring after a logical processor exits from C6 may incorrectly use the translation lookaside buffer (TLB) address mapping belonging to the other logical processor in the processor core.